Trace Impurity Review Table
Semiconductor programs should define restricted elements before sample production. The table helps procurement and process teams turn purity expectations into a measurable qualification file.
| Element | Typical Limit | Why Controlled |
|---|---|---|
| Fiber architecture | 2D / 3D route defined before quotation | Wrong architecture causes thread stripping, bolt shear, or creep under high-temperature load. |
| Density / open porosity | Project-defined density class and impregnation route | Density and porosity affect strength, oxidation sensitivity, and machining stability. |
| Oxidation exposure | Vacuum / inert baseline; coating or treatment reviewed if oxygen risk exists | C/C composite is not a substitute for atmosphere control when oxygen or water vapor is present. |
| Thread debris / edge chips | Visual and handling acceptance defined by buyer | Machined thread debris can interfere with torque, fixture cleanliness, and repeat assembly. |











