SiC Coated Dummy Wafer

Name: SiC Coated Dummy Wafer
Brand: SiC Graphite
SKU: sic-coated-dummy-wafer
Availability: InStock
Rating: 4.9 (24 reviews)

CVD SiC coated graphite dummy wafers used for thermal mass simulation, equipment calibration, and chamber burn-in. Cost-effective alternative to solid SiC dummies.

Target Buyer:Fab maintenance and equipment engineering.

SiC coated graphite dummy wafer for chamber calibration

Capability Highlights

Exact dimensional match to SEMI standards
High-purity SiC coating
Cost-effective thermal simulation

Typical Applications

Semiconductor Equipment Calibration
Chamber Conditioning

Engineering Focus

Thickness matching
Weight/thermal mass matching
Particulate control

Key Evaluation Matrix

Metric	Typical Range	Why It Matters
Dimensional Tolerance	+/- 0.02 mm	Must fit standard robotic handling systems.
Coating Uniformity	Thickness map or coupon check by project	Thin edges or pockets become the first failure point in corrosive epitaxy gases.
Base Graphite Match	CTE and density matched to CVD SiC coating	Poor substrate matching drives coating cracks, peeling, and exposed graphite.
Surface Finish	Ra target specified for wafer pocket or sealing surface	Surface finish affects wafer slip, particle risk, and thermal uniformity.

Engineering Datasheet

Product-Level Technical Specifications

Values below are RFQ planning targets, not blanket guarantees. Final acceptance criteria should be frozen against drawings, process conditions, equipment model, and buyer qualification requirements.

Parameter	Target / Typical Scope	Engineering Note
Wafer diameter	100 mm, 150 mm, 200 mm, or buyer-defined dummy wafer diameter	Diameter and edge profile must match the handling path, not only the process chamber.
Substrate route	Graphite core with CVD SiC coating on wafer-handling and process-exposed surfaces	The graphite core controls thermal mass and cost; the SiC coating controls surface cleanliness and chemical resistance.
Thickness and thermal mass	Buyer-defined thickness, mass target, and allowable tolerance by calibration use	Dummy wafers are often selected to simulate thermal behavior, so mass and thickness need explicit limits.
Notch / flat / edge profile	SEMI-style notch, flat, bevel, radius, or custom handling feature by tool requirement	Robot handling failures usually start at edge geometry, not at the center thickness.
Flatness and parallelism	CTQ flatness, bow, TTV, and parallelism where automated handling or contact uniformity matters	Flatness criteria should reflect the tool interface and chamber-contact surface.
Coating boundary	SiC coated front, backside, edge, notch, and masked surfaces defined before quotation	Coating thickness and edge coverage can affect final dimensions and robot clearance.

Trace Impurity Review Table

Semiconductor programs should define restricted elements before sample production. The table helps procurement and process teams turn purity expectations into a measurable qualification file.

Element	Typical Limit	Why Controlled
SiC coating purity	High-purity CVD SiC route with project-defined acceptance scope	Dummy wafers contact clean handling paths and process chambers where surface contamination matters.
Particles / chips	Visual acceptance and edge-chip limit defined by buyer	Edge chips or loose particles can cause handler alarms, chamber contamination, or wafer-contact damage.
Fe / Ni / Cr	Report or restrict by fab maintenance requirement	Metallic contamination can be included in qualification records for semiconductor chamber tools.
Clean packing condition	Separated, bagged, and protected wafer-style packing route	Dummy wafer surfaces can be scratched or contaminated during shipment if packed like ordinary machined parts.

RFQ Evidence Package

These records reduce ambiguity before sample approval and repeat-order release.

Dummy wafer drawing with diameter, thickness, notch or flat, bevel, radius, and datum references.
Coating map showing front, backside, edge, notch, masked, and wafer-contact surfaces.
Dimensional record for diameter, thickness, flatness, bow, TTV, and edge profile where required.
Visual inspection photos for edge chips, surface defects, coating finish, and wafer-contact areas.
Clean packing photos with separators, bagging, labels, and surface-protection method.

Equipment Compatibility Review

Compatibility should be treated as an engineering review, not a catalog claim. Equipment-family language helps buyers route the RFQ, while final production still depends on drawings, samples, coating allowance, and acceptance criteria.

Equipment Family	Compatible Part Scope	Buyer Validation Required
MOCVD and epitaxy reactors	SiC coated dummy wafers, calibration wafers, burn-in dummies, and thermal-mass simulation wafers.	Confirm wafer diameter, pocket or susceptor interface, temperature profile, coating boundary, and cleaning chemistry.
Plasma etch / RTP / carrier handling tools	Dummy wafers and coated carrier blanks for handling, calibration, and process conditioning.	Confirm robot handling interface, notch or flat requirement, thickness, TTV, flatness, and edge acceptance.
Custom semiconductor maintenance programs	Drawing-based SiC coated graphite dummies where solid SiC cost or availability is limiting.	Confirm current dummy wafer material, failure mode, lifetime target, acceptance report, and packing route.

Open full OEM compatibility matrix

Product Selection Logic

Decision Factor	Selection Logic	Buyer Check
Corrosive process gas	Choose CVD SiC coated graphite for MOCVD, epitaxy, HCl, NH3, or particle-sensitive wafer handling.	Specify gas environment, wafer size, equipment model, and lifetime target.
Coating feasibility	Deep pockets, blind holes, sharp edges, and hidden surfaces may need DFM changes before coating.	Ask for coating-thickness targets and note surfaces that must remain uncoated.
Substrate match	Base graphite must be chosen for CTE, density, and surface quality, not only machining cost.	Confirm CTE matching logic and first-article visual/coating inspection scope.

Manufacturing and QC Flow

Stage	Production / QC Checkpoint	Buyer Evidence
1. Coating DFM	Review pockets, blind areas, edges, masked surfaces, and coating-thickness target.	Marked drawing with coated, uncoated, and critical wafer-contact surfaces.
2. Substrate machining	Machine graphite substrate with CTE, density, and surface preparation matched to CVD SiC.	Base material selection note and pre-coating inspection record.
3. CVD SiC coating	Deposit dense SiC coating with attention to pockets, edges, and thermal-stress risk.	Coating thickness target and inspection method agreed before production.
4. Final inspection	Check visible defects, coating continuity, dimensions, and wafer-contact surfaces.	Inspection report, photos, or coupon result depending on order scope.
5. Clean export packing	Protect polished or coated surfaces from abrasion, fingerprints, and impact.	Individual wrapping, separators, and packing photos.

RFQ Checklist

Wafer diameter (e.g., 150mm, 200mm)
Required thickness
Notch or flat specifications

Risk Controls

Robot handling errors: Strict adherence to SEMI dimensional standards.

Product Gallery

Graphite substrate blank for coated dummy wafer manufacturing

Buyer FAQ

Are these safe for automated wafer handlers?

Yes, dimensions and edges are profiled to match standard silicon/SiC wafers.

What is the most common cause of SiC coating failure?

Early failure usually comes from substrate mismatch, coating shadow areas, sharp edges, or thermal cycling that creates cracks and exposes the graphite base.

Do all surfaces need the same SiC coating thickness?

No. Wafer-contact areas, gas-facing surfaces, edges, and masked interfaces should be marked on the drawing before the CVD coating route is finalized.

What evidence should a buyer request for coated parts?

Ask for agreed coating-thickness checks, visual defect inspection, critical dimensional checks after coating, and clean packing photos for sensitive surfaces.

Related Resources

Procurement Next Steps

Compare the full product portfolio before locking material architecture.
Match the part to a process solution for thermal-field and contamination constraints.
Review OEM capability controls for machining, coating, purification, and export packaging.
Send a drawing-based RFQ with process, material grade, tolerances, quantity, and delivery target.

Inquiry Email

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Include process, product type, drawing status, purity/coating target, dimensions, quantity forecast, operating conditions, and delivery date.

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