CVD SiC Coated Susceptor

Name: CVD SiC Coated Susceptor
Brand: SiC Graphite
SKU: cvd-sic-coated-susceptor
Availability: InStock
Rating: 4.9 (24 reviews)

Precision graphite susceptors with high-purity CVD SiC coating for MOCVD and silicon epitaxy. The coating helps improve resistance to corrosive gases and reduce carbon particle contamination risk.

Target Buyer:Process engineers in semiconductor fabs.

CVD SiC coated graphite susceptor for MOCVD epitaxy 1

Capability Highlights

Dense CVD SiC coating targets
Ultra-high purity
Thermal and chemical resistance for epitaxy environments

Typical Applications

MOCVD / Epitaxy
RTP (Rapid Thermal Processing)
LED / Power Device Manufacturing

Engineering Focus

Coating thickness uniformity
Surface roughness (Ra)
CTE matching between graphite and SiC

Key Evaluation Matrix

Metric	Typical Range	Why It Matters
Coating Thickness	80 - 120 µm	Ensures longevity against etching gases.
Coating Uniformity	Thickness map or coupon check by project	Thin edges or pockets become the first failure point in corrosive epitaxy gases.
Base Graphite Match	CTE and density matched to CVD SiC coating	Poor substrate matching drives coating cracks, peeling, and exposed graphite.
Surface Finish	Ra target specified for wafer pocket or sealing surface	Surface finish affects wafer slip, particle risk, and thermal uniformity.

Engineering Datasheet

Product-Level Technical Specifications

Values below are RFQ planning targets, not blanket guarantees. Final acceptance criteria should be frozen against drawings, process conditions, equipment model, and buyer qualification requirements.

Parameter	Target / Typical Scope	Engineering Note
Base material	High-purity isostatic graphite, grade selected by CTE and density	Substrate match reduces coating stress and exposed-graphite failure risk.
Coating type	High-purity CVD beta-SiC coating	Dense CVD SiC protects graphite from H2 / HCl / NH3 process exposure and particle release.
Coating thickness	Typical 80-120 um; project range can be reviewed	Thickness target depends on gas-facing surfaces, pocket geometry, and lifetime target.
Surface roughness	Ra target defined by wafer-contact or gas-facing surface	Pocket, sealing, and handling surfaces should not share one generic finish requirement.
Thermal expansion review	Base graphite CTE matched to coating route and operating cycle	Thermal mismatch is a common driver of cracks, edge lift, and premature coating failure.
Dimensional tolerance	Drawing-defined CTQ features; post-coating allowance required	Final fit should be checked after coating on pockets, OD/ID, grooves, and mounting faces.

Trace Impurity Review Table

Semiconductor programs should define restricted elements before sample production. The table helps procurement and process teams turn purity expectations into a measurable qualification file.

Element	Typical Limit	Why Controlled
Na / K	Buyer-defined ppm or ppb target	Alkali metals can contaminate high-value epitaxy and wafer-contact processes.
Al / Fe	Buyer-defined trace-metal limits	Common metallic contaminants that should be bounded before qualification samples.
Cr / Ni	Restricted where corrosion or alloy contamination matters	Transition metals can affect sensitive semiconductor process acceptance.
V / Ti	Project-specific limits for SiC and power-device programs	Often reviewed when substrate purity and coating purity are part of buyer qualification.

RFQ Evidence Package

These records reduce ambiguity before sample approval and repeat-order release.

Marked coating map showing coated, uncoated, masked, wafer-contact, and sealing surfaces.
First-article dimensional record for CTQ features after machining and coating.
Visual coating inspection photos and agreed thickness-verification method or coupon check.
Lot COA or project-defined trace-element table for substrate and coating qualification.
Clean handling and export packing photos before shipment release.

Equipment Compatibility Review

Compatibility should be treated as an engineering review, not a catalog claim. Equipment-family language helps buyers route the RFQ, while final production still depends on drawings, samples, coating allowance, and acceptance criteria.

Equipment Family	Compatible Part Scope	Buyer Validation Required
Silicon epitaxy reactors	Single-wafer, barrel, and pancake-style SiC coated graphite susceptors.	Confirm wafer size, gas-facing surfaces, AMAT / ASM / LPE-style interface, and drawing revision.
MOCVD and compound semiconductor reactors	Custom susceptors, trays, rings, plates, and gas-facing coated graphite components.	Confirm Aixtron / Veeco-style carrier geometry, pocket layout, rotation interface, and coating map.
RTP and annealing tools	Thermal-processing carriers and graphite fixtures where SiC coating is required.	Confirm ramp rate, thermal shock exposure, flatness requirement, and handling contact areas.

Open full OEM compatibility matrix

Product Selection Logic

Decision Factor	Selection Logic	Buyer Check
Corrosive process gas	Choose CVD SiC coated graphite for MOCVD, epitaxy, HCl, NH3, or particle-sensitive wafer handling.	Specify gas environment, wafer size, equipment model, and lifetime target.
Coating feasibility	Deep pockets, blind holes, sharp edges, and hidden surfaces may need DFM changes before coating.	Ask for coating-thickness targets and note surfaces that must remain uncoated.
Substrate match	Base graphite must be chosen for CTE, density, and surface quality, not only machining cost.	Confirm CTE matching logic and first-article visual/coating inspection scope.

Manufacturing and QC Flow

Stage	Production / QC Checkpoint	Buyer Evidence
1. Coating DFM	Review pockets, blind areas, edges, masked surfaces, and coating-thickness target.	Marked drawing with coated, uncoated, and critical wafer-contact surfaces.
2. Substrate machining	Machine graphite substrate with CTE, density, and surface preparation matched to CVD SiC.	Base material selection note and pre-coating inspection record.
3. CVD SiC coating	Deposit dense SiC coating with attention to pockets, edges, and thermal-stress risk.	Coating thickness target and inspection method agreed before production.
4. Final inspection	Check visible defects, coating continuity, dimensions, and wafer-contact surfaces.	Inspection report, photos, or coupon result depending on order scope.
5. Clean export packing	Protect polished or coated surfaces from abrasion, fingerprints, and impact.	Individual wrapping, separators, and packing photos.

RFQ Checklist

Provide 2D/3D drawings
Specify target coating thickness (e.g., 80-120µm)
Identify equipment model (e.g., LPE, Aixtron, Veeco)

Risk Controls

Coating micro-cracks: Strict CTE matching of base graphite and precise CVD temp profiling.

Product Gallery

CVD SiC coated graphite susceptor for MOCVD epitaxy 2

CVD SiC coated graphite susceptor for MOCVD epitaxy 3

CVD SiC coated graphite susceptor for MOCVD epitaxy 4

CVD SiC coated graphite susceptor for MOCVD epitaxy 5

SiC coated MOCVD susceptor for wafer processing 1

SiC coated MOCVD susceptor for wafer processing 2

SiC coated MOCVD susceptor for wafer processing 3

Buyer FAQ

What is the typical lifetime of your susceptors?

It depends on the process recipe, but dense coating and controlled base graphite selection can support longer intervals before recoating or replacement.

What is the most common cause of SiC coating failure?

Early failure usually comes from substrate mismatch, coating shadow areas, sharp edges, or thermal cycling that creates cracks and exposes the graphite base.

Do all surfaces need the same SiC coating thickness?

No. Wafer-contact areas, gas-facing surfaces, edges, and masked interfaces should be marked on the drawing before the CVD coating route is finalized.

What evidence should a buyer request for coated parts?

Ask for agreed coating-thickness checks, visual defect inspection, critical dimensional checks after coating, and clean packing photos for sensitive surfaces.

Related Resources

Procurement Next Steps

Compare the full product portfolio before locking material architecture.
Match the part to a process solution for thermal-field and contamination constraints.
Review OEM capability controls for machining, coating, purification, and export packaging.
Send a drawing-based RFQ with process, material grade, tolerances, quantity, and delivery target.

Inquiry Email

[email protected]

Email app

Include process, product type, drawing status, purity/coating target, dimensions, quantity forecast, operating conditions, and delivery date.

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+8618857971991

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